RISC-V 文献列表

收集整理关于RISC-V的公开发表文献（会议或期刊）

按年份排序的文献列表

索引	文献	链接
Delshadtehrani2018	L. Delshadtehrani, S. Eldridge, S. Canakci, M. Egele and A. Joshi. “Nile: A programmable monitoring coprocessor.” IEEE Computer Architecture Letters, 2018, 17(1), pp. 92-95.	[Web]
Tonetto2018	R. B. Tonetto, G. L. Nazar and A. C. S. Beck. “Precise evaluation of the fault sensitivity of OoO superscalar processors.” In proc. of Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2018, pp. 613-616.	[Web]
Ajayi2017	T. Ajayi, K. Al-Hawaj, A. Amarnath, S. Dai, S. Davidson, P. Gao, G. Liu, A. Rao, A. Rovinski, N. Sun, C. Torng, L. Vega, B. Veluri, S. Xie, C. Zhao, R. Zhao, C. Batten, R. Dreslinski, R. Gupta, M. Taylor and Z. Zhang. “Experiences using the RISC-V ecosystem to design an accelerator-centric SoC in TSMC 16nm.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Celio2017	C. Celio, P-F Chiu, B. Nikolic, D. A. Patterson and K. Asanovic. “BOOM v2: An open-source out-of-order RISC-V core.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Clark2017	M. Clark and B. Hoult. “rv8: A high performance RISC-V to x86 binary translator.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Collange2017	S. Collange. “Simty: Generalized SIMT execution on RISC-V.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Cook2017	H. Cook, W. Terpstra and Y. Lee. “Diplomatic design patterns: A TileLink case study.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Dennis2017	J. Dennis and W. Lim. “A RISC V extension for the Fresh Breeze architecture.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Eldridge2017	S. Eldridge, K. Swaminathan, N. Chandramoorthy, A. Buyuktosunoglu, A. Roelke, X. Guo, V. Verma, R. Joshi, M. Stan and P. Bose. “A low voltage RISC-V heterogeneous system.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Gray2017	J. Gray. “GRVI Phalanx: A massively parallel RISC-V FPGA accelerator framework, and a 1680-core, 26 MB SRAM parallel processor overlay on Xilinx UltraScale+ VU9P.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Kim2017	D. Kim, C. Celio, D. Biancolin, J. Bachrach and K. Asanovic. “Evaluation of RISC-V RTL designs with FPGA simulation.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Kurth2017	A. Kurth, P. Vogel, A. Marongiu, A. Capotondi and L. Benini. “HERO: Heterogeneous embedded research platform for exploring RISC-V manycore accelerators on FPGA.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Maas2017	M. Maas, K. Asanovic and J. Kubiatowicz. “Full-system simulation of Java workloads with RISC-V and the Jikes research virtual machine.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Matthews2017	E. Matthews and L. Shannon. “Taiga: A configurable RISC-V soft-processor framework for heterogeneous computing systems research.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Oh2017	H. Oh, Y. Lee, J. Park, M. Yang and Y. Paek. “Building hardware components for memory protection of applications on a tiny processor.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Roelke2017	A. Roelke and M. Stan. “RISC5: Implementing the RISC-V ISA in gem5.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Yu2017	Z. Yu, B. Huang, J. Ma, N. Sun and Y. Bao. “Labeled RISC-V: A new perspective on software-defined architecture.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Vega2017	L. Vega and M. Taylor. “RV-IOV: Tethering RISC-V processors via scalable I/O virtualization.” In proc. of Workshop on Computer Architecture Research with RISC-V (CARRV), 2017.	[URL] [PDF]
Asanovic2016	K. Asanovic, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitz, S. Karandikar, B. Keller, D. Kim, J. Koenig, Y. Lee, E. Love, M. Maas, A. Magyar, H. Mao, M. Moreto, A. Ou, D. A. Patterson, B. Richards, C. Schmidt, S. Twigg, H. Vo and A. Waterman. “The Rocket chip generator.” EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2016-17, 2016.	[URL] [PDF]
Celio2016	C. Celio, D. Dabbelt, D. A. Patterson and K. Asanovic. “The renewed case for the reduced instruction set computer: Avoiding ISA bloat with macro-op fusion for RISC-V.” EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2016-130, 2016.	[URL] [PDF]
Costan2016	V. Costan, I. Lebedev and S. Devadas. “Sanctum: Minimal hardware extensions for strong software isolation.” In proc. of USENIX Security Sympoisum, 2016.	[Web] [PDF]
Song2016	C. Song, H. Moon, M. Alam, I. Yun, B. Lee, T. Kim, W. Lee and Y. Paek. “HDFI: Hardware-assisted data-flow isolation.” In proc. of IEEE Symposium on Security and Privacy (S&P, Oakland), 2016.	[DOI] [PDF]