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RISC-V 双周简报 (2018-04-27)

要点新闻:

RV新闻

ISCA图灵讲座:计算机体系结构的新黄金时代

John L. Hennessy and David A. Patterson将在ISCA 2018上举办图灵讲座,题目是《A New Golden Age for Computer Architecture:Domain-Specific Hardware/Software Co-Design, Enhanced Security, Open Instruction Sets, and Agile Chip Development》。

在预告中,提到了以下几个关键领域来界定这个新时代。

  1. 面向高层次和特定领域的语言的软硬件协同设计(Hardware/Software Co-Design for High-Level and Domain-Specific Languages)
  2. 增强的安全性(Enhancing Security)
  3. 免费和开放的架构及其开源实现(Free and Open Architectures and Open-Source Implementations)
    1. 许多人可以同时利用RISC-V进行创新(Many people in many organizations can innovate simultaneously using RISC-V.)
    2. 指令集架构是模块化和可扩展的(The ISA is designed for modularity and extensions)
    3. 这个现代化的指令集是面向所有应用的,上至云端服务器,下至移动和物联网设备(It comes with a complete software stack, including compilers, operating systems, and debuggers, which are open source and thus also modifiable)
    4. 其包含完整的软件生态:包括编译器、操作系统以及调试器,而且是开源且可被修改的(This modern ISA is designed to work for any application, from cloud-level servers down to mobile and IoT devices)
    5. RISC-V是由有100多个成员启动的基金会推动的,以保证其长期的稳定性和持续演进(RISC-V is driven by a 100-member foundation that ensures its long-term stability and evolution)
  4. 敏捷芯片开发(Agile Chip Development)

Link: http://iscaconf.org/isca2018/turing_lecture.html

Processor Trace Group

UltraSoc 的 Gajinder 最近在 Mailing List 上宣布 Processor Trace Group的成立。Vice Chair是Ashling 的 Hugh Okeeffe。按照Group的Charter,这个小组会负责下列跟trace有关的介面和数据格式标准:

The group shall standardize both a hardware interface to the RISCV core and a packet/data format which will enable the development of commercial and open source trace encoders to be supported by any tools vendors. The interfaces are to provide enough information for: a. Instruction Trace. The interfaces should be suitable for in-order and out-of-order cores with extensions. The group will standardize the data format for: a. Compressed branch trace so that program flow can be reconstructed by debugging tools. The group’s progress shall be evaluated after one year at which time the charter may be revised if necessary to narrow the scope of effort.

小编讲古:先前,在Debug group的讨论中,常常讨论到trace的问题,毕竟这两者在设计上高度相关。但后来,Debug 和 Trace 分开了,因此目前的状况是Debug的Ratification 45天已经结束了。而Trace Group刚要开始。

Link: Processor Trace Group

QEMU 2.12 with RISC-V

QEMU 2.12 最近发佈了。这是第一个内含RISC-V的正式版本!

Link: QEMU 2.12

技术讨论

通过兼容测试并不代表无错(compliant is not validated)

在关于缓存操作指令的讨论中,Allen Baum解释了RISC-V兼容性测试的一些概念:

Link: Allen Baum的邮件

不同范围的 memory protection and translation

最近,又有讨论提到Page size为什麽要是4kB的问题。和先前的结论一样,是因为mprotect & mmap 将page size的信息给了上层软体,导致 Porting 将十分複杂。不过在这讨论中,有另外一个有趣的议题。那就是能不能用不同范围的memory protection 和 translation 来增加Scalability 呢?的确有人做过这样的研究和实作,像是Mondrian Memory Protection[1],以及Intel的 sub-page protection[2]。

目前RISC-V的 memory protection 一个是在 M-mode 有最多16个区域,每个区制至少4byte。另一个是在U mode的 Page table上,由RWX 来控制每个页(4kb)。未来有没有机会出现更好又向后兼容的方案呢?小编有点期待。

Links:

代码更新

Linux kernel 4.17 rc3 update

在4.17 rc3 的 pull中,修復了几个config的细节。包括 PIE, DMA的Kconfig, 和 include的问题。

A Kconfig cleanup to select DMA_DIRECT_OPS instead of redefining it in arch/riscv. The removal of asm/handle_irq.h, which doesn’t exist, from our arch header list. The addition of “-no-pie” the link rules for our VDSO-related files, which fixes the build on systems where PIE is enabled by default.

小编感觉比较有趣的部分是还在 review 的 Perf 和 generic free_init_mem。期待这些patch能早日完成review。

Link: LKML

生态系统

seL4在RISC-V上初步移植成功

seL4是在高可靠领域非常知名的微内核,整个系统通过形式验证,用数学证明保证其软件没有缺陷。

Data61在seL4 Version 9.0.1 Release中包含了RISC-V的移植,移植目前还很初步。

Initial prototype RISC-V architecture port. This port currently only supports running in 64-bit mode without FPU or or multicore support on the Spike simulation platform. There is no verification for this platform.

Links:

实用资料

RISC-V QEMU Part 2: The RISC-V QEMU port is upstream

Michael Clark 在这篇中详细介绍了最新QEMU port的使用方式。

Link:QEMU part2

市场相关

SemiWiki: SiFive’s Design Democratization Drive

Camille Kokozaki在SemiWiki上发表文章《SiFive’s Design Democratization Drive》,报道和讨论了SiFive CEO Naveed Sherwani在GSA Silicon Summit上所提出的一些观点和想法。

他首先举了Instagram成功的例子,认为其成功的要素是在现有成熟和庞大的基础架构上完成了其最小可行性产品(MVP:minimum viable product)。之后其引申到了半导体行业,指出目前我们的MVP需要的大约数百万美元,以及9-24个月还不算Tapeout的时间,以及需要非常多的专业人士参与。他为我们业界提出了一个目标:

他提出了几条路径,包括:

之后Naveed Sherwani提出了SiFive的Vision和目前的状态。

小编:SiFive的发展速度的确非常迅速,这和他们采用敏捷的硬件开发方法是密不可分的。中国的半导体要在现有领域超车,敏捷和速度也是必不可少的能力之一。在这一点上我们需要向SiFive学习。

Link: SiFive’s Design Democratization Drive

Rambus发布基于RISC-V的安全核心CryptoManager Root of Trust

Rambus发布了其安全核心_CryptoManager Root of Trust_,一个可编程的硬件核心而且其内建的一个定制的RISC-V CPU。安全处理器会创建一个孤立的系统,隔离并保护主处理器上的敏感代码。

The CryptoManager Root of Trust is based on a custom 32-bit RISC-V CPU designed specifically to provide a trusted foundation for secure processing in the core and system. The RISC-V CPU runs signed code modules called containers, which include permissions and security-related metadata. These containers can implement standard security functionality, or complete customer-specific security applications, including key and data provisioning, security protocols, biometric applications, secure boot, secure firmware update, and many more. Part of the comprehensive CryptoManager Security Platform that includes embedded cores, key provisioning infrastructure and infield services, the Root of Trust provides the highest level of end-to-end security at all stages of the chip lifecycle for applications like IoT, automotive, sensors, and connectivity.

小编:有了RISC-V这样的开放的处理器架构,更多厂商能够在不依赖第三方CPU core vendor的情况下更好的推出其有竞争力的产品。

Link: Rambus Launches CryptoManager RISC-V Root of Trust Programmable Secure Processing Core

Alibaba收购中天微

Alibaba最近宣布收购了杭州的另一家具有自主CPU架构的中天微(C-Sky)。值得注意的是中天微是RISC-V的白金会员,所以未来中天微在RISC-V领域的发力也值得我们期待。

Of course, the obvious question among semiconductor market observers in the West is whether the global embedded market might be already cornered by dominant CPU processing cores such as ARM and MIPS. And what about the rising tide behind RISC-V?

Qi, at that time, told us: “China needs to work on the development of ‘core technologies,’ and we think our embedded CPU is one of them.” As for RISC-V, Qi called it “promising” and told us last year, “We are looking into it for our solutions for 64-bit CPU cores.” C-Sky is a platinum member of the RISC-V Foundation.

Link: Alibaba Adds Embedded CPU Core Designer

新奇事物

Hackday.io的Itsy-Chipsy项目

Hackerday.io上有人发起了项目:Itsy-Chipsy: Make your own $100 chip。这个项目背后的团队似乎是Open-V,一个32-bit RISC-V开源处理器的团队,尽管这个项目在CrowdSupply上的众筹并未成功,但是可以看到这个团队持续在努力中。

Itsy-Chipsy提供一种叫做“multi-block service”的服务,希望将流片的成本进一步降低。似乎是在MPW的芯片上,首先提供一些基本的供电/IO/外设的模块,然后将剩余面积分块,然后分开出售。

Link: Itsy-Chipsy: Make your own $100 chip

暴走事件

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招聘简讯

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整理编集: 宋威、黄柏玮、郭雄飞


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