CNRV

为推广RISC-V尽些薄力

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RISC-V 雙周簡報 (2018-03-16)

要點新聞:


RV新聞

RISC-V調試標準公開征求意見45天

RISC-V Debug Spec的草案下載 address :https://git.io/vxqzS#riscv-debug-spec.pdf

RISC-V Debug Spec的公開征求意見期為45天,從2月22日至4月8日。

如果關心調試系統並對標準有任何問題及意見,請務必在這個郵件列表:https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/ymcXwjPw16I/knQQS1dtBAAJ 或在https://github.com/riscv/riscv-debug-spec/issues 提出您的問題和意見。

這將是RISC-V基金會第一個從工作小組遞交的標準extension草案。 因為是第一次,所以整個流程還不是非常明確。 現在已知的部分流程如下:

這個還是暫時的流程,關於45天公布期之後流程,RISC-V基金會將很快在riscv.org上公布細節。 不過,已經確認,這45天是RISC-V標準extension草案唯一的向所有人征集意見的機會。 如果基金會投票通過,草案成為標準,則很難再有大的改動。 CNRV的RISC-V愛好者多次在微信群討論了調試,特別是最近針對semi-host的部分。 請相關愛好者務必抓住機會。如果意見足夠多,還是有可能被接受甚至重新一輪45天意見征集的。


生態發展

RISC-V 的 QEMU port upstreamed

經過八個版本的patch,最近 Sifive的 Michael Clark 把QEMU的risc-v port 推進主線了! 期待之後更多軟體的發展。

Link: Commit of RISC-V port

RISC-V 的 gdb port upstreamed

Embecosm 的 Andrew Burgess 最近將 risc-v port 推進 gdb 的主線了! 期待 risc-v 的基礎軟體架構能越來越完整!

Link: gdb: Initial baremetal riscv support

libffi 的risc-v port upstreamed

libffi 是 OpenJDK 以及 Dalvik 等軟體的基礎。Stefan O’Rear 最近將libffi 的 risc-v port成功推入主線。

Link:New RISC-V port

OpenJDK Zero 的 risc-v port

Ed Nevill 最近開始了OpenJDK Zero 的 risc-v port。期待risc-v 軟體生態能早日支持 java。

Link:Add RISC-V support to Zero


技術討論

RISC-V微控制器規範(microprocessor profile)

GNU MCU Eclipse的作者Liviu Ionescu最近提出一個非常詳細的微控制器規範, 用以明確定義微控制器的外設、時鐘、啟動過程、ABI等等硬軟體相關信息。 這對統一RISC-V微處理器在嵌入式和IoT領域的應用有很重要的意義。

現在的問題是,該微控制規範和Alex Bradbury和SiFive正在定一個64位系統的ABI規範不兼容。 希望他們能迅速協調並制定出一個兼容方案。

微控制器規範的一級目錄:

Explicit cache control指令提案

Explicit cache control 指令提案 (第3版, 第4版, 第5版)

有時候不得不佩服外國人的堅持。 繼去年8月份提出的第4版提案,Jacob Bachmeyer 最近又提出了 explicit cache control 指令的第5版!

explicit cache operation 指令使用了FENCE指令還未用的指令空間。

第5版中的指令定義:(有區別的加粗)

** explicit cache control 對於高性能計算系統和嵌入式系統是非常重要的。** ** 提案還沒有被收納入RISC-V正式指令集,看起來是因為對一些指令的副作用,特別是帶破壞性的指令,還無法完全清除。** ** RISC-V指令集仍然堅持,所有對 cache 的 explicit control 必須對軟體透明。也就是說,這些指令只能是hint, cache 一定可以不遵照執行。**

具體的討論可著重看這麽幾段:


實用資料

胡同學的《大道至簡——RISC-V架構之魂》系列文章

蜂鳥處理器的作者胡振波同學最近發表了系列文章《大道至簡——RISC-V架構之魂》來深入淺出的介紹了RISC-V相關的內容,有興趣的同學歡迎移步它的公眾號。

LWN 上介紹 RISC-V 和 RISC-V Fedora port 的系列文章

Richard.W.M.Jones 開始在LWN上連載一系列關於risc-v 和 risc-v fedora的文章。目前,第一篇關於risc-v的介紹已經公開。Richard在文中介紹了risc-v 軟體的現況,以及risc-v 指令設計中的一些特點,像是:

Macro-op fusion v.s. Instruction extension

Although the architecture is (by design) simple, boring, and similar to others that have gone before, one interesting area is the approach to complex instructions such as specialized instructions for string handling, video decoding, or encryption.

Some of these may be implemented in future extensions. For others, the designers have expressed a preference not to add complex instructions to the specification but instead to rely on macro-op fusion for performance. (Note there is a patent claim on a limited version of this technique, although it expires in 2022.) Processors are expected to detect sequences of simpler instructions that together perform some complex operation (e.g. copying a string) and fuse them together at run time into a single more efficient macro operation. How this wish will meet reality is yet to be seen, but it does mean that, for now, writing a RISC-V emulator is relatively easy because there are only simple instructions.

Richard表示下一篇將開始介紹Fedora 是怎麽被移植到risc-v中的。敬請期待。


行業視角

Heterogeneous Hubbub

SemiEngineering的Ann Steffora Mutschler最近發表短評《Heterogeneous Hubbub: The combination of heterogenous architectures and RISC-V is encouraging new tool support for SoC teams》。文中主要是對Krste Asanovic做的一些訪談。

教授首先提到了過去常見的一個通用處理器(比如ARM)加一個專用處理器的做法。而現在,RISC-V的可extension性能夠結合兩者的優勢,從而減少不必要的開銷。

“Really, the best energy efficiency you’re going to get for anything that has significant compute is going to be adding new functions, custom instructions to tackle that application domain. We made the base RISC-V ISA lean and clean, and easy to extend to add those special functions on the side. If you think about in the market previously, you basically had to pick either a general core that ran lots of software or some kind of configurable core that didn’t run all the software and usually you’d have to pair these two together. And then what happens is you’re shifting data between the two of them going between the general core and the accelerator; that also takes a lot of energy. Low power designs, the current systems most of the power and energy goes into shifting data around, so you want to minimize that traffic if you can.”

在採訪中,教授提到了他們對RISC-V指令集的簡潔性上所作出的努力。

Asanovic said, “I like to tell people we worked really, really hard to keep it simple. It’s not easy. We iterated many times on the design. We started in 2010 and froze the base ISA in 2014. Along the way we did about a dozen implementations, including the software, the compilers, the OS, everything, to try and trim the fat, and really get it as lean as we could, while still being efficient. I think people are surprised how well it performs given how small the instruction set is. The way we view it is that effort you save on designing the base core, you can spend on your power optimization. You have a given design effort budget for any project, and you can either spend it implementing and verifying a more complex instruction set or you can spend it tuning your design to lower the power.”

小編:相信很多是對於RISC-V都是抱著一種Yet Another RISC ISA的態度,那麽RISC-V真的又好又簡單麽?恐怕要你們使用者和處理器架構師來回答了?

Link: Heterogeneous Hubbub

EPI:歐洲雄心勃勃的Exascale級超算計劃

似乎這也是為什麽下次的RISC-V Workshop會在Barcelona的BSC-CNS(Barcelona Supercomputing Center舉辦。European Processor Initiative (EPI),一個由20多個歐洲的廠商組成的合作聯盟將會得到約1.2億歐元的經費支持用戶開發超算用的處理器。

Europe has an ambitious plan to become a main player in supercomputing. The EuroHPC initiative is a joint undertaking with as one of its goals to construct an exascale supercomputer based on European technology. One of the core parts is a processor. Although there are several processor-related research projects, it is only now that an effort has started to build a production HPC processor with industry quality. This is done as part of a 120 million euro Framework Partnership Agreement (FPA) that has been awarded to a consortium of 23 partners. We talked to the project coordinator Philippe Notton from Atos to learn more about the “European Processor Initiative” as the project is called.

而RISC-V自然是一個上佳的選擇。當然,RISC-V在HPC領域還恐怕還需要不斷改進才能滿足其需求。

One of the goals of Europe is to create European technologies. This is also a key point for us. Because such a design cannot be 100% European in the end, since we have potential issues with the available factories for instance. We know that Europe is no longer producing memories, as another example. We are trying to bring as much European DNA as possible into the system. This makes the core selection challenging because there is no off-the-shelf core which is purely European. We have some micro-controllers technology coming from Europe but they are not powerful enough for this class of HPC design. That is why, as part of this consortium, we are going to start our own processor development which is based on RISC-V, and develop some IP’s and ecosystem around it. We do not start from zero, because there is some instruction set and elements which are ready. Unfortunately, it is not at HPC production level yet and it will take a couple of generations.

小編:國產超算領域的工程師們,你們怎麽看?

Link: http://primeurmagazine.com/weekly/AE-PR-03-18-87.html


行業新聞

QuickLogic加入基金會

eFPGA廠商QuickLogic最近加入了RISC-V基金會。

Link: QuickLogic joins RISC-V Foundation


暴走事件

三月

五月

六月

招聘簡訊

CNRV提供為行業公司提供公益性質的一句話的招聘信息發布,若有任何Architecture、IC設計、軟體開發的招聘信息,歡迎聯系我們!


整理編集: 宋威、黃柏瑋、郭雄飛 繁體 translation 維護者:黃柏瑋


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