RISC-V Debug Spec的草案下载地址：https://git.io/vxqzS#riscv-debug-spec.pdf
RISC-V Debug Spec的公开征求意见期为45天，从2月22日至4月8日。
如果关心调试系统并对标准有任何问题及意见，请务必在这个邮件列表：https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/ymcXwjPw16I/knQQS1dtBAAJ 或在https://github.com/riscv/riscv-debug-spec/issues 提出您的问题和意见。
这将是RISC-V基金会第一个从工作小组递交的标准扩展草案。 因为是第一次，所以整个流程还不是非常明确。 现在已知的部分流程如下：
这个还是暂时的流程，关于45天公布期之后流程，RISC-V基金会将很快在riscv.org上公布细节。 不过，已经确认，这45天是RISC-V标准扩展草案唯一的向所有人征集意见的机会。 如果基金会投票通过，草案成为标准，则很难再有大的改动。 CNRV的RISC-V爱好者多次在微信群讨论了调试，特别是最近针对semi-host的部分。 请相关爱好者务必抓住机会。如果意见足够多，还是有可能被接受甚至重新一轮45天意见征集的。
经过八个版本的patch，最近 Sifive的 Michael Clark 把QEMU的risc-v port 推进主线了! 期待之後更多软件的发展。
Link: Commit of RISC-V port
Embecosm 的 Andrew Burgess 最近将 risc-v port 推进 gdb 的主线了! 期待 risc-v 的基础软件架构能越来越完整!
libffi 是 OpenJDK 以及 Dalvik 等软件的基础。Stefan O’Rear 最近将libffi 的 risc-v port成功推入主线。
Link:New RISC-V port
Ed Nevill 最近开始了OpenJDK Zero 的 risc-v port。期待risc-v 软件生态能早日支持 java。
现在的问题是，该微控制规范和Alex Bradbury和SiFive正在定一个64位系统的ABI规范不兼容。 希望他们能迅速协调并制定出一个兼容方案。
- Memory Map
- The Startup Process
- Exceptions and Interrupts
- Control and Status Registers (CSRs)
- Hart Control Block (
- Hart Interrupt Controller (
- Device Control Block (
- Device Real-Time Clock (
- Device System Clock (
- Device Watchdog Timer (
- Embedded ABI (EABI)
- RTOS Support Features
- Appendix A: Improvements upon RISC-V privileged <— Read Me First!
- Appendix B: History
- Appendix C: Contributing
有时候不得不佩服外国人的坚持。 继去年8月份提出的第4版提案，Jacob Bachmeyer 最近又提出了直接缓存操作指令的第5版！
直接缓存操作对于高性能计算系统和嵌入式系统是非常重要的。 提案还没有被收纳入RISC-V正式指令集，看起来是因为对一些指令的副作用，特别是带破坏性的指令，还不是完全清除。 RISC-V指令集仍然坚持，所有对缓存的直接操作必须对软件透明。也就是说，这些指令只能是hint，缓存一定可以不遵照执行。
Richard.W.M.Jones 开始在LWN上连载一系列关于risc-v 和 risc-v fedora的文章。目前，第一篇关于risc-v的介绍已经公开。Richard在文中介绍了risc-v 软件的现况，以及risc-v 指令设计中的一些特点，像是：
Macro-op fusion v.s. Instruction extension
Although the architecture is (by design) simple, boring, and similar to others that have gone before, one interesting area is the approach to complex instructions such as specialized instructions for string handling, video decoding, or encryption.
Some of these may be implemented in future extensions. For others, the designers have expressed a preference not to add complex instructions to the specification but instead to rely on macro-op fusion for performance. (Note there is a patent claim on a limited version of this technique, although it expires in 2022.) Processors are expected to detect sequences of simpler instructions that together perform some complex operation (e.g. copying a string) and fuse them together at run time into a single more efficient macro operation. How this wish will meet reality is yet to be seen, but it does mean that, for now, writing a RISC-V emulator is relatively easy because there are only simple instructions.
SemiEngineering的Ann Steffora Mutschler最近发表短评《Heterogeneous Hubbub: The combination of heterogenous architectures and RISC-V is encouraging new tool support for SoC teams》。文中主要是对Krste Asanovic做的一些访谈。
“Really, the best energy efficiency you’re going to get for anything that has significant compute is going to be adding new functions, custom instructions to tackle that application domain. We made the base RISC-V ISA lean and clean, and easy to extend to add those special functions on the side. If you think about in the market previously, you basically had to pick either a general core that ran lots of software or some kind of configurable core that didn’t run all the software and usually you’d have to pair these two together. And then what happens is you’re shifting data between the two of them going between the general core and the accelerator; that also takes a lot of energy. Low power designs, the current systems most of the power and energy goes into shifting data around, so you want to minimize that traffic if you can.”
Asanovic said, “I like to tell people we worked really, really hard to keep it simple. It’s not easy. We iterated many times on the design. We started in 2010 and froze the base ISA in 2014. Along the way we did about a dozen implementations, including the software, the compilers, the OS, everything, to try and trim the fat, and really get it as lean as we could, while still being efficient. I think people are surprised how well it performs given how small the instruction set is. The way we view it is that effort you save on designing the base core, you can spend on your power optimization. You have a given design effort budget for any project, and you can either spend it implementing and verifying a more complex instruction set or you can spend it tuning your design to lower the power.”
小编：相信很多是对于RISC-V都是抱着一种Yet Another RISC ISA的态度，那么RISC-V真的又好又简单么？恐怕要你们使用者和处理器架构师来回答了？
Link: Heterogeneous Hubbub
似乎这也是为什么下次的RISC-V Workshop会在巴塞罗那的超算中心举办。European Processor Initiative (EPI)，一个由20多个欧洲的厂商组成的合作联盟将会得到约1.2亿欧元的经费支持用户开发超算用的处理器。
Europe has an ambitious plan to become a main player in supercomputing. The EuroHPC initiative is a joint undertaking with as one of its goals to construct an exascale supercomputer based on European technology. One of the core parts is a processor. Although there are several processor-related research projects, it is only now that an effort has started to build a production HPC processor with industry quality. This is done as part of a 120 million euro Framework Partnership Agreement (FPA) that has been awarded to a consortium of 23 partners. We talked to the project coordinator Philippe Notton from Atos to learn more about the “European Processor Initiative” as the project is called.
One of the goals of Europe is to create European technologies. This is also a key point for us. Because such a design cannot be 100% European in the end, since we have potential issues with the available factories for instance. We know that Europe is no longer producing memories, as another example. We are trying to bring as much European DNA as possible into the system. This makes the core selection challenging because there is no off-the-shelf core which is purely European. We have some micro-controllers technology coming from Europe but they are not powerful enough for this class of HPC design. That is why, as part of this consortium, we are going to start our own processor development which is based on RISC-V, and develop some IP’s and ecosystem around it. We do not start from zero, because there is some instruction set and elements which are ready. Unfortunately, it is not at HPC production level yet and it will take a couple of generations.
2nd CARRV 第二次CARRV workshop(Computer Architecture Research with RISC-V ) 将在6月2日和ISCA 2018共同举办。
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