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RISC-V 双周简报 (2018-03-02)

要点新闻:

RV新闻

Embedded World上的RISC-V

今年在德国举办的Embedded World上RISC-V大放异彩。

多个RISC-V的伙伴参展并且发表演讲,当中还包含一个独立的RISC-V Session。

更多信息见基金会网站页面: RISC-V At Embedded World 2018

GreenWaves发布GAP8芯片和GAPUINO开发板

GreenWaves Technologies是一家法国的无晶圆半导体初创公司,致力于开发基于RISC-V的IoT应用处理器,使其能够应用于由电池驱动的嵌入式设备,并在低功耗、低速率和特定计算能力场景下可靠工作长达数年。

公司的第一款产品 GAP8为终端设备提供了一种超低功耗计算解决方案,能够对多种内容丰富的信息源(如图像,声音和动作)进行处理,内置的多核处理单元和神经网络加速器让GAP8在物联网应用场景内游刃有余。在能效方面,在执行某些任务时能够做到15-20倍优于市场现有微处理器。

参考文章:GAP8 performance versus ARM M7 on Embedded CNNs

GreenWaves Technologies最近发布了售价199欧元的基于GAP8芯片的开发板 - GAPUINO。包含一个GAPUINO开发板,一个低功耗QVGA摄像头模块以及一个多种传感器集成板。

GAPUNIO

GAPUINO提供了一个基于GAP8并行运算处理器的开发平台,可以用于处理图像、声音和振动等输入信号。开发板的参考样例包括关键字识别(语音)、行人检测或人脸检测等。GAP8还支持较为复杂的电源管理方案,从而实现长达数年的电池续航时间。

GAP8 SDK包含3个部分:

  1. RISC-V GNU工具链以并支持添加到GAP8中的扩展指令
  2. 对于主控制核心目前有两种OS支持
    • PULP OS:做为PULP项目的一部分(基于事件/线程的操作系统)
    • Arm Mbed OS(将Mbed OS项目移植用于RISC-V / GAP8)
  3. 多核CLUSTER开发工具: GAP8 AutoTiler,其能够自动生成执行L2或外部存储器之间的数据移动的代码,并且充分利用GAP8多核架构优势。同时包含GAP8代码生成器库,该库已拥有使用GAP8 AutoTiler开发的不同算法,包括CNN层,FFT,矩阵运算,FIR滤波器等等

GAP8 Arch

GAP8的架构中有8个并行的RISC-V核心可以用于做并行处理(SPMD),除了八个核心之外还包含一个Hardware Convolution Engine,这些核共享I$。芯片由TSMC 55nm工艺制造,面积7x7mm2。

小编点评:

在这个靠堆硬件吸引眼球的时代,如何平衡功耗、成本和计算能力?如何在新的AI浪潮面前迅速推出产品?如何在提供硬件的同时也提供高层次工具?如何利用RISC-V架构来提高产品竞争力?我想GreenWave交出了一份不错的答卷。

GAP8相关报道和评论

GreenWaves Technologies Unveils GAP8

“GAP8 differs radically from the flurry of other AI focused processors, which target either far more complex applications that can’t be battery powered, or much narrower application spaces. Instead, GAP8 is precisely positioned at the crossroads of the AI, IoT and MCU worlds. The autonomous operation enabled by GAP8 dramatically reduces the deployment and operating costs of image, sound and vibration sensing devices, enabling an unprecedented scale of adoption,” said Loïc Liétar, co-founder and CEO of GreenWaves Technologies. “Furthermore, building on the RISC-V and PULP open source projects has allowed us to bring to market radical innovation with an outstanding capital efficiency at a speed that allows us to promptly serve customer demand.”

GAP8’s ultra-low power operation enables use cases such as

  • Always-on face detection with a few mWs of power
  • Indoor people counting / presence detection with years of autonomy
  • Sub $15 machine vision and voice control solutions for consumer robotics
  • Single chip processing for 4 microphone voice capture and 10-word speaker independent keyword spotting

AI Comes to Sensing Devices

They include an extended RISC-V instruction set architecture to pack more operations into each cycle, an energy optimal sign-off frequency, hardware synchronization, eight-core parallelization, a fast turn-on/switch off function achieved by putting the power management unit inside the chip, a shared instruction cache and a hardware convolution engine.

More specifically, hardware synchronization is important because, for fine-grain loops, synchronization dispatched to the eight cores could burn up to 50 percent of the sequential computing. This would drastically limit efficiency in parallelization, said Liétar. “Doing this synchronization in HW removes this limitation,” he said.

IoT apps processor boasts eight RISC-V cores

The part features eight RISC-V cores combined with a convolution hardware accelerator. It also has a separate core with an independent frequency and voltage domain. Croome said: “One side of the chip looks like an MCU; the other side is the RISC-V cluster, which shares instruction caches.”

Interestingly, Greenwaves has developed the part on an apparent shoestring, having only raised €3.1m in August 2017. “It’s a small amount of money for a start up,” Croome noted, “but we’re using open source components. We couldn’t have used anything other than RISC-V cores because that would have needed more investment.”

GreenWaves Puts Another Spin on IoT Chips

GreenWaves is a 16-person startup with headquarters outside scenic Grenoble, France. Their first (and so far, only) product is GAP8, a microcontroller intended to bring CNN smarts to cheap, battery-powered IoT edge devices. The chip combines some familiar open-source hardware with some unfamiliar, proprietary circuitry to create something the company thinks will be smarter and more power-efficient than anything the world’s many and varied Arm licensees can conjure up.

Rather than using the ubiquitous Arm Cortex-A or -M cores, GreenWaves relies on the potentially ubiquitous RISC-V design. The benefits here are twofold: RISC-V is free (as in free beer), and RISC-V permits user-defined extensions. GreenWaves took advantage of both characteristics to build itself a complex multicore MCU that’s tweaked for image, audio, and sensor processing. The idea is to make the edge-node processor smart enough that it doesn’t have to upload raw data to a smarter device upstream. Do your data-capture, analysis, filtering, and massaging right at the point of collection and you’ll save yourself time, money, and power.

感谢陈杰和张垚提供信息

Debug spec 进入45天的 public review

经过一年左右,debug spec最近进入了45天的 public review期间,按照基金会的规则,45天完后就会做ratification,标准就会确定下来。对debug spec 有兴趣的朋友可以针对debug spec给予反馈。这是RISC-V 标准中,第一个进入public review的部分。随着越来越多多核risc-v cpu 出现,小编也期待memory model 的部分能早日进入45天的public review。

开源硬件更新

OPENPULP - 另一个多核RISC-V 平台

PULP 团队最近开源了他们的多核平台OPENPULP,也就是先前tape out的 Mr.Wolf。OPENPULP以架构上来说,是由一个小核控制八个大核以及加速器来运算。更重要的是,这是除了rocket以外,另一个多核的RISC-V平台。PULP团队列出了OPENPULP的几个特点像是:

开源软件更新

risc-v gdb patch v2

在工具链(gcc,llvm,gdb,glibc,binutils,newlib)中,risc-v的 gdb port一直是个缺乏关注的环节,embecosm 的 Andrew Burgess 最近开始针对gdb 提交patch。期待 gdb 也能早日合併主线。

QEMU patch v7

来自 SiFive 的 Michael Clark 持续的在提交 QEMU patch,并在最近针对合併主线,做了一次port submission。

Fedora/RISC-V: Runnable stage 4 disk images

Richard 持续的推进fedora bootstrap的情况下,目前的 fedora 有 bootable disk images了。按照Richard整理的结果,目前这个port包含:

如果想要尝试一个简单的linux distribution,可以使用这个 port。除了Fedora以外,debian这端,也有非常多的bug report,看来两个linux distribution 在risc-v 这块都有不少进展。

技术讨论

由支持运行时关闭RVC支持而引发的一系列问题

RVC,即RISC-V得压缩指令集,是一个非常有用的RISC-V指令级扩展。 在支持RVC的处理器上,有可能需要临时关闭RVC支持。 其具体操作就是清除misa.C比特。 在清除misa.C比特后,处理器应该严格执行32比特指令并要求指令对齐32比特地址。

最先由形式化工作组提出,关闭RVC操作会引发未定义的行为。 这种未定义的行为简单来说有两个:

这里大家在激烈争论的问题是,如果出现这种情况,到底算哪一条指令出现了异常。比如对第一个问题,到底是算CSRW指令错误,还是后续的指令非对齐错误?

根据现在的修改预案,解决方案大致如下:

这里就有些不对称的问题了。mret也是跳转,却总是正确完成,报后面指令的地址错误。而jmp/branch却会报当前指令的错误。 这里的问题是,如果mret指令会引发异常,将会破坏硬件的异常处理,有可能导致不能在异常处理后正确返回异常之前的优先级。 jmp和branch指令立即发生异常,则是为了能更好的调试。 如果jmp和branch将pc设为非对齐地址,而报后面指令错误。发生错误时很难发现错误的原因是跳转错了地址。

RDCYCLE的意义

鉴于最近Krste在ISA标准中解释了hart的定义,Liviu Ionescu提出了新问题: “那么,RDCYCLE读取到的是一个处理器(processor core)执行的时钟周期数是不是不准确了呢?” 结果,为了解释这个,Krste准备又要在标准里加一大段解释了。 解释太长,具体看这里:https://github.com/riscv/riscv-isa-manual/issues/140#issuecomment-368856451

简单说呢,其实是这样的: 首先,RDCYCLE读到的是一个处理器core执行的时钟周期数而不是一个hart的周期数。 原因是因为一般的SMT处理器并不能严格获得一个hart所执行的周期数。 但这并不是一个问题。RDCYCLE本来就只是一个单调随时间正向增长的计数器。 这里的确是一个不准确的定义,但是这个定义的确也很难准确。 不准确的定义不代表就不能被定义。

进一步的缓存预取计划

Max Hayden Chiz在hw-dev列表中进一步细化了关于为Rocket-Chip(Rocket和BOOM)添加缓存硬件自动预取功能的计划, 并号召有时间的人一起来完成。 具体的计划可见邮件列表

进一步的讨论中又冒出了很多好点子。比如说Jacob提出我们可以找到32个寄存器中使用较多的几个寄存器,然后用硬件预测寄存器的步长。如果发现寄存器有固定步长变化,同时被用于访问内存,则可用于指导自动缓存预取(stride prefetch)。同时,为了防止预取被用于缓存侧信道攻击,预取的缓存块应该放入单独的缓存空间,只有当缓存块真的被访问才进入一级缓存。

代码更新

即将到来新的一轮Rocket-Chip变量名变更

一个设计的成熟度有时候其实依赖于很简单的东西,比如频繁使用的变量名在前后版本中保持一致。 不过,Rocket-Chip的设计者们决定,他们又要更名了。 这回:

希望这回更名能持续的久一点。

实用资料

All Aboard, Part 10: How to Contribute to the RISC-V Software Ecosystem

Palmer在这篇 blog 中整理了 RISC-V software eco 目前的状况。有兴趣採用risc-v的同学可以参考。

市场相关

IAR Systems加入RISC-V基金会

国内朋友比较熟悉的嵌入式IDE厂商IAR最近加入了基金会,让我们期待IAR未来在RISC-V的支持。

“The RISC-V technology and ecosystem are currently evolving rapidly and there are a lot of exciting innovation going on connected to the RISC-V community,” comments Anders Holmberg, Director of Corporate Development, IAR Systems. “We have customers currently looking at working with RISC-V in upcoming design projects, and they have expressed a need for high-performance commercial tools with professional technical support. By adding our leading tools to the ecosystem, we respond to our customers’ needs, and also create new business potential within the RISC-V community.”

Link: IAR Systems commits to bring leading development tools to the growing number of RISC-V users

Imperas发布用于快速评估Linux的RISC-V RV64GC High-Performance Extendable Platform Kit

Imperas发布了可以用来让开发人员评估RISC-V Linux系统的平台开发包。

Imperas virtual platform products provide for a broad range of software verification and profiling capabilities. Model code coverage and instruction coverage enable an effective measure of software verification quality to be established. A broad range of profiling tools, including timing performance and power consumption, allow for effective quality metrics to be established, prior to hardware availability. An advanced debug solution is also included with advanced features designed specifically for complex multi-core software.

Link:

CEVA加入RISC-V基金会并且声称在其解决方案中使用RISC-V处理器

CEVA 最近加入了RISC-V 基金会,并在这篇新闻中介绍他们在CEVA 的 Wifi IP 中使用risc-v core 的经验。

CEVA’s experience with RISC-V

Like these companies, CEVA has been intrigued by the potential of RISC-V, especially in regards to our RivieraWaves Wi-Fi and Bluetooth IPs (Figure 1). These communication technologies require a small processor to execute the protocol stacks and our aim was to create an integration-ready reference platform that offers our customers freedom in the choice of processor. In terms of requirements, the horse-power needs are modest, even for advanced Wi-Fi configurations, since the IPs have been architected for very low power operation. The brief calls for a low gate count, power efficient, mature processor, with a familiar, commercial-grade software development environment that can produce die-saving compact code. The design must be suitable for easy deployment (at full speed) in FPGA and in ASIC/ASSP and it must have a legal framework compatible with our business of licensing IP.

The RISC-V processor implementation is perfectly matched to typical IoT device requirements in terms of performance and die cost, with a Coremark/MHz figure of 2.44 in a gate count of under 20Kgates. Blending perfectly with the low power architecture of the RivieraWaves IP, the RISC-V based Bluetooth platforms offer the industry’s lowest clock frequency and most power efficient Bluetooth low energy and Bluetooth dual mode solutions. For heavier data loads, the RivieraWaves Wi-Fi RISC-V platforms are the world’s smallest fully-integrated solutions, and scale from basic 1x1-11b-1Mbps up to 2x2-11ac/ax MU-MIMO-1201Mbps. These pre-integrated RISC-V based platforms significantly reduce the development time and bill-of-materials for CEVA’s customers, allowing for rapid product development and market introduction.

Link:

Express Logic的基于RISC-V的工业级X-Wave IoT平台

Express Logic发布了其工业级X-Wave IoT平台,平台基于ThreadX RTOS平台并提供Microsemi Mi-V RISC-V处理器的完整的支持。

ThreadX RTOS通过了多个安全认证,小编认为这是其主要的优势。

In addition to the performance and size advantages of the X-Ware IoT Platform, Express Logic’s ThreadX, FileX, and NetX Duo have attained the highest level of safety certifications. They include IEC 61508 SIL 4, IEC 62304 Class C, ISO 26262 ASIL D, EN 50128 SW-SIL 4, UL 60730-1 Annex H, CSA E60730-1 Annex H, IEC 60730-1 Annex H, IEC 60335-1 Annex R, and IEC 60335-1 Annex R, 1998.

Link: Express Logic’s X-Ware IoT Platform® Brings Industrial-Grade IoT Support to RISC-V Architecture

会议征稿

第八届 RISC-V Workshop Call for Papers

在西班牙举办的第八届RISC-V workshop开始徵稿了! 有兴趣的同学可以赶快把握机会!

暴走事件

二月

三月

五月

六月

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整理编集: 宋威、黄柏玮、郭雄飞


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