CNRV

为推广RISC-V尽些薄力

View the Project on GitHub

RISC-V 双周简报 (2017-09-14)

RV新闻

RISC-V LLVM port

Andes Technology (晶心科技) 最近释出他们开发中的 RISC-V LLVM port, 共释出 LLVM, Clang 以及 compiler-rt, 该版本基于 LLVM 5.0 开发, 目前支援 RV32IMAC 以及 RV64IMA 的编译, 且已通过多项开源及商业测试套件, 具有相当程度的稳定度与可靠性, 他们表示希望透过这次的开源能够加速 RISC-V 社群上 LLVM 相关开发及避免各方的重複开发, 并且及早让社群有个稳定可用的 LLVM Toolchain.

相关讨论: https://goo.gl/grWHSe

相关 repo:

RISC-V linux port 第八版

Palmer最近提交了第八版, 目标在下月进入linux-next,并期望能在 4.15 进入主线。(小编:4.14来不及进实在很可惜。期待越来越多的kernel工作者能帮忙review。)

FireSim在Amazon F1上部署Rocket-chip仿真

FireSim是加州伯克利大学新成立的关于使用FPGA加速数据中心的应用平台。他们最近将Rocket-chip的多核模型部署到Amazon的F1 FPGA加速平台。 这个多核模型支持1-8核的时钟精确仿真模型(小编:应该就是Rocket-chip的FPGA实现),并且拥有网卡实现。

FireSim平台:http://fires.im/

FireSim demo v1.0 https://aws.amazon.com/marketplace/pp/B0758SR46G

第一届基于RISC-V的体系结构研讨会(CARRV 2017)报告安排新鲜出炉

第一届基于RISC-V的体系结构研讨会(Workshop on Computer Architecture Research with RISC-V) 即将在10月14日作为MICRO 2017的子会议在美国波士顿举行。 会议内容现已在 https://carrv.github.io/ 公布,其中有很多有意思的报告,希望会后能有文章资源下载。

RISC-V的Formal Specification工作组

这个小组正在制定 RISC-V 的 Formal specification。目前已经有五个组织,尝试着制定和实现。使用的语言包括L3、Verilog HDL、Haskell以及BSV。

目前 Rishiyur所带的小组正要整合这几个 specification 和实现。

有兴趣的朋友可以加入这小组参与讨论,或参考这些repo:

  1. Prashant Mundkur (SRI); written in L3. Repo.
  2. Clifford Wolf (individual): written in Verilog. Repo and slide.
  3. Adam Chlipala and group (MIT): written in Haskell.
  4. Rishiyur Nikhil (Bluespec, Inc.): written in BSV. Repo.
  5. Team of Peter Sewell in Cambridge : written in SAIL. Repo.

Link: https://goo.gl/iCUq1A

技术讨论

现有GCC编译器支持的编译目标类型

继上期关于bare-metal交叉编译器的讨论,Michael Clark 很好地总结了当前riscv-unknown-elf-gcc编译器支持的编译目标和相应的参数配置。

RISC-V Newlib ELF Toolchain Link options:

  1. Default: crt. libc, libgloss (binaries work with the riscv-pk and riscv-isa-sim, or in riscv-linux)
    • riscv-unknown-elf-gcc
  2. Alternative default: crt, libc and libgcc (will fail to link unless libgloss POSIX system call stubs are implemented)
    • riscv-unknown-elf-gcc -nostdlib -lc -lgcc
  3. crt, libc, libnosys and libgcc (will link but POSIX calls return -ENOSYS)
    • riscv-unknown-elf-gcc -nostdlib -lc -lnosys -lgcc
  4. “Default bare metal” linkage (user supplies _start symbol, default text address 0x10000)
    • riscv-unknown-elf-gcc -nostdlib -nostartfiles
  5. “Actual bare metal” linkage (user supplies _start symbol and a linker script)
    • riscv-unknown-elf-gcc -nostdlib -nostartfiles -Wl,-T,myprog-link.ld

相关讨论: https://goo.gl/gcrqcw

代码更新

GCC规定函数栈默认对齐16字节

除了RV32E之外,无论是RV32还是RV64,函数栈都将默认对齐16子节(128比特)。 社区对此决定显然有不同意见,一边是嵌入式设计者主张使用更小的对齐大小,比如RV32使用8字节, 而另一边则是兼容性系统的设计者主张使用较大的对齐大小,以支持双精度甚至4倍精度或者以后可能遇到的扩展。

最后的讨论结果是,函数栈的默认对齐其实是ABI的一部分。ABI本身是为了函数库共享和二进制一致性而产生的。 这些功能其实都只在较兼容的系统上才有意义。对栈对齐大小敏感的嵌入式系统往往都使用静态编译或不遵守ABI,所以ABI的设计应该服从兼容性系统的要求。 那么,GCC的栈对齐大小定义为16字节是合理的。不过为了能让嵌入式系统使用自己的(非标准的)对齐大小, GCC将增加-mpreferred-stack-boundary参数来自定义栈对齐。

具体讨论:

GCC将主动忽略所有非标准的扩展指令

RISC-V指令集允许用户定义自己的非标准扩展指令集。 这些指令集可以被定义成参数用于GCC的-march选项,但是必须以x开头。 GCC会自动忽略所有以x开头的非标准扩展指令但是将参数传递给汇编器。 这样就可以支持用嵌入式汇编的方法通过修改汇编器来使用非标准扩展。

The RISC-V ISA allows custom ISA extensions to be defined by users. These extensions must come after all the standard extensions, and must start with ‘x’. This patch allows these custom extensions to be passed via the ‘-march’ flag and ignores them – we don’t plan on supporting any custom extensions in GCC, so I think that’s always the right thing to do. These extensions will be passed to the assembler, which is expected to have either been modified to support the extension or produce an error.

详情请见 riscv-gcc PR #91: https://git.io/v5umy

实用资料

RISC-V 101 webinar

SiFive 正在针对 Embedded software programmer 举办一系列的webinar。总共有三场。9/12已经举办过第一场,是针对RISC-V ISA本身的介绍。有兴趣入门RISC-V的可以听听看。第一场的录影在此。((小编:好险有录影。因为办的时间对中国真的有点晚,1:30am….)

行业视角

Breakfast Bytes Blogs: Naveed Sherwani Takes the Reins at SiFive

来自Cadence的Paul McLellan采访了SiFive新任的CEO并且发表了博客文章。

Naveed sees part of his job is to change the culture of the semiconductor industry. As he put it:

Do we want to leave behind an industry like the railways, still important but mature, or leave a vibrant, innovative ecosystem?

He sees the challenge to make hardware companies more like software companies, where you can get a company to a minimum viable product (MVP) with very low capital, and only then, if it is successful, go and raise the money. …

He also wants to move to a “no support” model like software companies. Software companies, especially open source, don’t help their customers. Customers help each other, with chat rooms, meetups, and so on. That is how they can deliver free versions of their software. He pointed out that Cadence could deliver some of these small startup companies software that is free but with no support. These companies have time but not money. Then the company would pay when they were ready for production. That way the up-front costs of getting a fabless semiconductor company off the ground are not a barrier to it ever happening. As Naveed put it:

If 10,000 downloads and only 10% are successful, that is still 1,000 companies for the existing ecosystem to make money from.

I remain a bit skeptical that this can be done. The industry is littered with the carcases of companies who assumed that they could dramatically lower the costs of doing design and make good money on relatively low-volume designs. Every FPGA company had, and then gave up, on taking designs that were already essentially done and hardening them. Semiconductor manufacturing is a mass-production process. This means that designs that are not intrinsically high volume have needed to be aggregated. The only really successful way of doing that aggregation has been the FPGA, where the generic silicon runs in high volume and the user customizes it themselves. Even if Naveed is successful at persuading the EDA and IP suppliers to forgo up-front money, there is still non-trivial manufacturing costs for prototypes and significant investment for volume manufacturing. Hardware is simply not software, which can truly be delivered, once written, without any significant cost.

Link: http://t.cn/RpTK49p

市场相关

SiFive and UltraSoC partner to accelerate RISC-V development through DesignShare

SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC’s embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. UltraSoC’s debug and trace functionality will enable users of the Freedom platform to access a wide variety of tools and interfaces to use in their developments.

CNRV社区活动

9月9日,上海组织了一次小型的线下交流活动,大家就RISC-V的发展、安全、操作系统等方面展开了深入讨论。

暴走事件

九月

十月

十一月

招聘简讯

CNRV提供为行业公司提供公益性质的一句话的招聘信息发布,若有任何体系结构、IC设计、软件开发的招聘信息,欢迎联系我们!


整理编集: 宋威,郭雄飞,黄柏玮

贡献者:Kito Cheng


欢迎关注微信公众号CNRV,接收最新最时尚的RISC-V讯息!

CNRV微信公众号


知识共享许可协议
本作品采用知识共享署名-非商业性使用-相同方式共享 3.0 中国大陆许可协议进行许可。