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RISC-V 双周简报 (2017-07-20)

RV新闻

Syntacore的SCR1处理器更新至Privileged Spec 1.10和User Spec 2.2

On 16/07/2017 08:26, Alexander Redkin wrote:

Our open-source RISC-V RV32I[MC] SCR1 implementation is updated to comply with the current draft of the 1.10 privileged spec: https://github.com/syntacore/scr1

It’s distributed under permissive apache 2.0-based license and we encourage academic/educational use (can expect best-effort support).

Feel free to refer to the talk by one of the SCR1 developers at the recent 6th RISC-V workshop for additional details: https://riscv.org/2017/05/6th-risc-v-workshop-proceedings

Linux內核第六版

推动Linux内核的主线方面,Palmer Dabbelt于2017年7月11日向内核邮件列表递交了RISC-V Linux Port v6。目前的情况看來合并到4.13已经不可能,期待4.14时能合并到主线。

rv8 更新

Michael Clark正在做一個RISC-V to x86-64的指令级虚拟执行器,目前在一些小的benchmark已經比QEMU快了2.5倍。

I added some new benchmark stats for the RISC-V to x86-64 binary translation engine. We are now in the order of ~2.5X QEMU user mode binary translation performance on a small set of benchmarks.

RISCY BUSINESS 频道

Mio Iwakura在youtube开了一个关于RISC-V的频道(http://riscy.tv/)。他正尝试做一个跟RISC-V有关的toolchain,同时也把阅读Spec的过程拍成影片。

技术讨论

提议向RISC-V B扩展指令集(bit操作扩展)添加选择(MUX)指令

Michael Clark提议向RISC-V B扩展指令集添加一条MUX指令:

mux rd, rs1, rs2, rs3

完成选择(C语言 ` ? : ` 操作符)的功能:

rd = rs1[0] ? rs2 : rs3

该提议的原因有几点:

反对的意见也很多:

讨论中覆盖的其他问题(知识点):

User spec 2.2

The standard software calling convention uses x1 as the return address register and x5 as an alternate link register. The alternate link register supports calling millicode routines (e.g., those to save and restore registers in compressed code) while preserving the regular return address register.

定义x5为可选链接寄存器是为了支持millicode,可以理解成一小段辅助代码。在使用(跳转到)这种辅助代码时,我们不希望影响到原有代码的上下文,包括链接寄存器(x1)的值。这种情况下,可以使用x5为链接寄存器而不将x1压栈,同时x5为临时寄存器,也不需要保护。

更详细的解释请参看这个stackoverflow的问答:JAL: what is the alternative link register x5 for?

Explicit Cache instruction 重启讨论

虽然这个话题沉寂了很久,最近,它又引起了广泛的讨论。Andes的工程师几天前在邮件列表裡提出了他们对于Cache instruction的想法。他们的提案是用VA based,而且有区分I$和D$。相反的,Guy和Jacob先前所提的都是range-based,而且没有区分I$和D$。有兴趣的可以参考看看。

On Tue, Jul 18, 2017 at 3:24 AM, chuanhua.chang chuanhua.chang@gmail.com wrote:

The cache-control instructions we are thinking about are summarized in the following table:

    VA Based    
  icache   dcache  
  invalidate (+ unlock)   invalidate (+ unlock)  
      writeback  
      writeback & invalidate (+ unlock)  
  lock   lock  
  unlock   unlock  

The PIN or lock operation should have a return status to indicate its success, so that this operation will not lock out all ways of a multi-way cache. And a simple implementation can decide not to support cache locking and always return “fail” for the lock operation.

代码更新

Rocket-chip代码结构调整

Freechipsproject/rocket-chip经历了一次较大的结构调整。 其中包括:

(hcook)

  • Refactors package hierarchy to remove uncore and prepend freechips.rocketchip
  • Removes legacy ground tests and configs
  • Removes legacy bus protocol implementations
  • Removes NTiles
  • Adds devices package
  • Adds more functions to util package

修正一级缓存一致性错误

对称多处理(SMP)的Rocket-chip在运行Linux时会出现挂起错误,该错误可能是由于一级缓存在接到Probe请求(当二级缓存需要询问一级缓存相关缓存块状态时向一级缓存发送的询问请求)处理不当。该错误现在应该被纠正。

(aswaterman)

  • Handle TL errors in I$
  • Fix D$ probe bug
  • Add option for shared L2 TLB (disabled by default)

Rocket-chip的二级缓存缺失

大概在今年4月,由于TileLink2的使用,原来Rocket-chip的二级缓存被暂时移除。 现在SiFive的Wesley终于回答了sxu55在4月份问的问题: 由于原有的二级缓存使用了老的TileLink接口,而我们(SiFive)一直都没有可用于产品的新二级缓存,现在不能提供二级缓存的支持。

(Wesley)

Unfortunately, we never had a production-ready L2. Also, the previous L2 spoke a now obsolete version of TileLink. At present there is no L2 in the repository. :-(

安全点评

自从2000年以来在x86和armv7/arm64硬件平台上GNU/Linux的攻防历史来看,RISC-V是有机会借鉴x86和armv7/arm64的一些经验

比如对于x86芯片以及芯片组来说:

另外,x86平台上的Linux内核一直以来安全问题都没有得到改善。这跟x86子系统是由Linus Torvalds本人维护有关,Linus认为性能更重要。虽然ARM子系统由ARM公司把控,推进安全上也相对较快,但依然没有很好的解决安全问题。这两大平台的历史教训都应该引起RISC-V的注意和警觉。

今年4月份Don A. Bailey公开了一个由内核Supervisor mode运行的程序映射一段代码进而任意执行Machine mode的代码的漏洞利用。该漏洞应该已经被最新的Privelege spec 1.10中的物理内存保护机制(PMP)修复。

RISC-V仍然在快速发展中,在安全方面应该广泛参考以往处理器和操作系统的问题,仔细考量。

by Shawn(citypw)

微群热点

众包RISC-V中文普及书

《步步惊芯》的作者雷思磊提出了撰写一本RISC-V中文普及书的建议并起草了提纲的草稿。编辑部会持续跟踪这个事件…

RISC-V讨论群成立子群

RISC-V[0]群已爆棚,RISC-V[1]群开放邀请,不要错过哦~

行业视角

ARM vs RISC-V: A Game Theory perspective

Prakash Mohapatra, PraxThoughts, Jul. 07, 2017

“… I strongly believe in the democratic business model of ARM, in which all the stakeholders of the fabless ecosystem makes money. In my earlier blog posts, I have shared my insights on why Intel, although having huge cash flow, failed to penetrate the smart phone SoC market. I believe the primary reason is that it was a competition between ARM’s ecosystem and Intel (with its vertically integrated business model).

Ecosystem enables network effects to take place, and it is difficult to challenge incumbents who hold important positions in the over-all value chain. Currently, ARM occupies such a position in the embedded and IoT market. For RISC-V to challenge ARM, the former must create an extensive ecosystem around its ISA. With an open-source ISA, RISC-V has opened up the value-chain further by going one step back from ARM, which earns revenue from licensing its ISA. So, RISC-V has more potential to create a symbiotic ecosystem. …”

RISC-V and The Birth of the New Computer Architecture Ecosystem

Ricardo Anguiano, Jul 10, 2017

“Other open source tool and OS efforts have failed to get their changes accepted upstream because, while the work required is highly technical, it also involves understanding how to work with the existing codebase and the existing development community. Essentially you want to understand and adhere to the existing norms of the project’s development community and make your case that your implementation is also technically sound. To paraphrase an old friend, you want to make it easy for the existing project maintainers to give you an “A” and accept your proposed changes.

市场相关

SiFive的双月新闻

The SiFive Download

SiFive在新聞中整理了跟RISC-V有關的訊息,像是各類型的報導。

Andes的每季新闻

Andes in Sight Vol. 3, No.2

Andes在新聞中介紹了他們的NX25以及Andestar V5。

暴走事件

八月

十月

招聘简讯

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整理编集: 宋威,郭雄飞,黄柏玮

贡献者:Shawn


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