CNRV

为推广RISC-V尽些薄力

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RISC-V 双周简报 (2017-07-06)

RV新闻

第七届RISC-V研讨会征稿启事

下届RISC-V研讨会将会在加州硅谷举行,由西部数据承办,现已开始征集论文和演讲(25分或12分),时间定为11月28-30日。

The 7th RISC-V workshop will be hosted by Western Digital in Milpitas California on November 28-30, 2017.

Talks can be of two lengths (25 minutes and 12 minutes), and talk presenters are expected to also participate in the poster session to allow extended discussion. All poster presenters will give a 3-minute poster preview.

Submission Guidelines:

Submission abstracts should consist of at most two pages in pdf format, and must include the title, authors, and affiliations. Additional material can be appended to the submission that the organizers will review at their discretion. The submission website allow selection of the desired presentation format (25 minute talk, 12 minute talk, 3 minute poster preview).

Submission Website: https://www.softconf.com/h/riscv7thwkshp/

Important Dates:

  • Submission Deadline: September 17, 2017
  • Author Notification: October 1, 2017

Program Committee:

  • Dan Lustig, NVIDIA
  • Dave Ditzel, Esperanto Technologies
  • Dejan Vucinic, WD
  • G S Madhusudan, IIT Madras
  • Robert Mullins, University of Cambridge
  • Silviu Chiricescu, BAE Systems
  • Yungang Bao, ICT/CAS
  • Yunsup Lee, SiFive

Send questions relating to the program (prog_comm@workspace.riscv.org) and questions relating to conference operation to the executive director, Rick O’Connor (rickoco@riscv.org).

RISC-V Linux第四版

SiFive的Palmer Dabbelt本周提交了第四版的RISC-V的Linux Patch,祝他好运~

SeL4 on SMP

Hesham最近完成了SeL4的SMP支持。他在Spike中使用了2到9个核来测试。这是他的博客和一些关于sel4 on RISC-V的介绍。

支持RISC-V的处理器实现统计

VectorBlox的Guy在DAC会议前对现有支持RISC-V指令集的处理器实现做了个统计,投影片里面有一些有趣的结果可以参考。

来自Bespoke Silicon Group的RISC-V文档

UCSD的Michael B. Taylor教授所领导的Bespoke Systems Group小组整理了不少RISC-V的文档,包括虚拟内存和协处理器接口RoCC。 此外,他们也用RISC-V做了一些很有趣的设计

My team recently completed a TSMC 16-nm tapeout with 5 Linux-capable Rockets and 496 RISC-V 32IM cores in a tiled manycore array. 4 Rockets connect via RoCC to the manycore array, and the 5th uses RoCC to talk to a neural network accelerator.

RISC-V的官方每月新闻

RISC-V基金会开始发布每月新闻

UltraSoC宣布成为业内首个支持RISC-V Trace功能的厂商

UltraSoC, the leading developer of embedded analytics technology, today announced that it has developed processor trace support for products based on the open source RISC-V architecture. The company has developed a specification for processor trace that will be offered for adoption by the RISC-V Foundation as part of the open source specification. In addition, UltraSoC today becomes the first ecosystem participant to offer an implementation of this functionality.

UltraSoC’s implementation of RISC-V processor trace functionality will be available in Q42017.

MicroSemi发布Windows版本的基于Eclipse的开发平台

Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the release of its SoftConsole version 5.1, the world’s first available Windows-hosted Eclipse integrated development environment (IDE) for designs utilizing RISC-V open instruction set architectures (ISAs) such as RV32I. SoftConsole, Microsemi’s free software development environment enabling rapid production of C and C++ programming language designs for its field programmable gate arrays (FPGAs), will be showcased at the Design Automation Conference (DAC) in a presentation highlighting its open architecture, low power and development capabilities using RISC-V soft central processing unit (CPU) cores.

“With the majority of Microsemi FPGA designers utilizing a Windows platform for their development efforts, SoftConsole v5.1 not only supports our RISC-V soft CPU cores to enable designs with our highly secure and reliable FPGAs, but it can also be used for any RV32I standard ISA extensions,” said Tim Morin, director of marketing at Microsemi, who will be presenting on the subject at DAC on June 20. “This product release broadens the RISC-V ecosystem for those developing on Windows machines, and leverages our leadership position as we continue investing in this architecture to provide customers dependable, long-term roadmap support.”

技术讨论

合并AUIPC和JALR来实现长跳转

很多人正在讨论合并AUIPC和JALR指令(instruction fusion)来实现直接长跳转的可能性。ARM的AArch64指令集已经使用了指令合并技术,比如,cortex-A72就有实现它。此外,这个讨论串解释了RISC-V User level 2.2 specification对支持返回地址栈(return address stack,分支预测的技术之一)的设计考量

微群热点

新版RISC-V Dhrystone跑分变差

胡振波同学发现RISC-V gcc 7.1.0版本生成的代码比6.1.0版本dhrystone跑分变差,详见SiFive Forum & GitHub Issue

为什么我编个rocket-chip/boom总是很慢?

宋威答:如果你还在用虚拟机的话,还是乖乖裸装Linux吧,会快很多。

RoCC这种指令格式,gcc/gas如何是否支持?

参见: Github IBM rocc-software

什么样的JTAG Dongle可以用来Debug SiFive/Freedom/RocketChip呢?

群主答:只要有TCK/TDI/TDO/TMS就可以,要是有SRST更好。其实更重要的是你的JTAG Dongle要被openocd支持。

chisel/firrtl在编译阵列时时间非常长

相关讨论请参见:

我在玩ZYNQ上的rocket-chip,有什么建议?

群主答:切换到sifive freedom平台吧,那个有点老了。

胡总评价ARC和RISC-V

“从技术上来讲,ARC的指令集设计的应该是极端的极致了,我从没有见过这么极致的指令集,什么delay slot,zero hw loop等等那都是最基本的,还有很多特定的指令。所以把指令的密度推到了几乎risc架构的极限。然后在硬件设计上也用到了很多奇技淫巧,几乎把cpu设计艺术推到了极限。当然代价就是在硬件设计和验证上付出了相当的efforts。但是在结果各项指标上我还没见过有什么risc core的指标能够超过arc的。

这个极致的哲学和riscv是截然相反的,riscv的哲学就是“简单简单简单-够用就好够用就好–这个太复杂了不要不要”。

市场动向

暴走事件


Editor: 宋威,郭雄飞,黄柏玮


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