CNRV

为推广RISC-V尽些薄力

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2018 RISC-V巴塞罗那 Workshop特别报道 (1)

Welcome Address & Foundation Overview, Rick O’ Connor

RISC-V Members

RISC-V Growth

State of the Union: RISC-V, Krste Asanovic

A system us minimally RISC-V-ISA-compliant if it runs claimed RISC-V unprivileged code correctly.

A platform specification provides tight constraints on system configuration and options to support software ecosystem. Platform compliance test provided by relevant ecosystem.

  • Develope consensus around best security practice.
  • Develope and publish RISC-V security road map.
  • Create repos and new attack trends, threats and countermeasures.
  • Identify top 10 open challenges in security.

The State of RISC-V Software, Palmer Dabbelt & Arun Thomas

Open Standard Work

RISC-V LLVM Porting

Vector ISA Proposal Update, Roger Espasa

Rishiyur: Formal spec update

RISC-V Memory Consistency Model Task Group Update, Daniel Lustig

RVWMO in a Nutshell 1

RVWMO in a Nutshell 2

Unleashing the Power of Data with RISC-V, Martin Fink

Unleashing the Power of Data with RISC-V

RISC-V Debugging: Custom ISA Extensions, Multicore, DTM Variants, Markus Goehrle

Jeremy: GDB for RISC-V

Simon: software environment

HiFive Unleashed: World’s First Multi-Core RISC-V Linux Dev Board, Yunsup Lee

SiFive U540

SiFive Unleash

HiFive Unleashed Expansion Options and Capabilities, Ted Marena

SiFive U540 and MicroSemi

Simulating Heterogeneous Multi-node 32-bit and 64-bit RISC-V Systems Running Linux and Zephyr with the Open Source Renode Framework, Michael Gielda

Debian GNU/Linux Port for RISC-V 64-bit, Manuel Fernandez Montecelo

Fedora on RISC-V, Richard Jones

Fedora on RISC-V

Smallest RISC-V Device for Next-Generation Edge Computing, Seiji Munetoh

Smallest RISC-V Chip


作者:宋威

编辑:CNRV编辑部


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